AutoSVA
I write SystemVerilog Assertions for RTL code.
AutoSVA is a SystemVerilog Assertions tool developed by ubiwork.co that aids in writing SystemVerilog Assertions for RTL code. It provides prompt starters and supports Python as one of its tools, offering assistance in generating various SVAs for specific RTL scenarios. With its primary focus on automating the process of writing SystemVerilog Assertions, AutoSVA streamlines the task and enhances efficiency in RTL code verification.
How to use
To make the most out of AutoSVA, follow these steps:
- Access the AutoSVA tool developed by ubiwork.co.
- Familiarize yourself with the prompt starters provided for generating SVAs.
- Utilize the Python tool supported by AutoSVA for seamless SVA generation.
- Apply the generated SystemVerilog Assertions to RTL code.
- Enjoy the optimized process of writing SVAs for increased RTL code verification efficiency.
Features
- Automated SystemVerilog Assertions generation for RTL code
- Support for Python tool to facilitate SVA creation
- Comprehensive prompt starters for various SVA scenarios
- Enhanced efficiency in RTL code verification
Updates
2023/11/09
Language
English (English)
Welcome message
Hello! Need help with SystemVerilog Assertions?
Prompt starters
- Explain an SVA for FIFO full.
- Generate SVA for FIFO write.
- Create an assertion for FIFO overflow.
- How to reference internal signals in SVA?
Tools
- python
Tags
public
reportable